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1. LSYSTEM - Overview The LSYSTEM digital logic simulation software package is a CAD tool which allows users to (1) describe the composition and structure of a digital system comprising combinational logic elements, sequential logic elements and memory devices, (2) verify the system's logic function, and (3) simulate and display the timing diagram for specified logic signals. LSYSTEM allows complete flexibility in the use and generation of logic element model libraries. Logic elements can be modelled as gate level primitives or at a higher functional level. Gate and functional level models can be freely mixed in both the model libraries and logic network simulations. - Logic networks are described in a form similar to SPICE. - Node names can be alphanumeric up to 16 characters long. - 10k Maximum nodes. - Maximum logic elements is dependent on system memory. - 500 maximum user defined gate and functional primitives. - 500 user defined macros. - 256 maximum internal states for sequential primitives. - Comprehensive default primitive library supplied. - Range of TTL and CMOS macros supplied. - Zero propagation delays allowed with gate and functional elements. - Resolution of 1nS during simulation. - Primitive element delays may be set from 0 to 4S. - Primitive element strengths can be set from 0 to 100%. - Macro nesting up to 20 levels deep. - Unlimited number of include files. - Include file nesting to 20 levels deep. - Full network description syntax checking. - Rigorous declaration checking for correct number of nodes etc.. - Errors reported in a user friendly manner. - Fast and accurate simulation cycle. - Flexible digital waveform post-simulation graphics processor. PLEASE NOTE the LSYSTEM specification presented above referees to the Production version of the software. Files LS1.DOC, LS2.DOC and LS3.DOC describe the production software - the SHAREWARE version of LSYSTEM is a full working version of the package BUT is restricted in the size of logic network it can simulate. SEE file README.1 for the SHAREWARE details. 2. Specification of the computer system required to run LSYSTEM Computer: IBM PC/XT/AT family. Memory: 640k ram required. Floppy disk: at least two 5.25" DSDD 360k capacity. Hard disk: optional. Numeric coprocessor: not required. Printer: 9 or 24 pin dot matrix. Operating system: MS/PC DOS 2.0 upwards. Mouse: optional. Graphics adapters, one of the following or 100% clones:- IBM Colour Graphics Adapter (CGA). IBM Enhanced Graphics Adapter (EGA). IBM Video Graphics ARRAY (VGA). Hercules Monochrome Graphics Adapter. 3. Installing LSYSTEM Ensure that the CONFIG.SYS file on your boot disk ( whether hard or floppy ) contains the lines :- FILES = 20 BUFFERS = 20 Copy all files from the set of LSYSTEM disks into your chosen directory. The LSYSTEM software is now ready to be used for digital logic simulation. In this publication it is assumed that the LSYSTEM software resides in a directory called LSYSTEM on the C drive. If you are using floppy disk drives see Appendix A for installation instructions. 4. Using LSYSTEM 4.1 The Simulation cycle Three programs are used to complete the simulation cycle:- (1) COMPILE.EXE, (2) SIMULATE.EXE and (3) WAVEFORM.EXE. To simulate and study the performance of a digital logic network over a specified time period, several steps are required, these are:- - Describe the structure and logic elements which form the digital network, specify all input signals and output test points, in file FILE.NWK using a suitable NON-DOCUMENT text editor. - Compile the network description using COMPILE.EXE. - Simulate the network using SIMULATE.EXE. - View the logic network signal waveforms using WAVEFORM.EXE. - Inspect tabular results in file FILE.RLT. Various files are required (or generated) at each stage, they are as follows, where FILE is the logic network name chosen:- COMPILE.EXE FILE.NWK --+ FILE.INF -- Information I FILE.EXP -- Macro expansion I FILE.LST --+ I FILE.MOD I- DATA files I FILE.TRA I I FILE.NAM---+ +---------------- Network description SIMULATE.EXE FILE.FNC --+ FILE.MOD I FILE.TRA I FILE.NAM I---------------- Data I WAVEFORM.EXE FILE.GRA I FILE.NAM --+ INPUT FILES OUTPUT FILES Fig. 1 outlines the complete simulation sequence and the relationship between the input and output files. SEE PRINTED USER GUIDE FOR DIAGRAM A minimum simulation cycle, assuming a digital network description had been generated, using for example the PCWRITE word processor, in file test.NWK, would proceed as follows ( ignore the DOS prompt, this is included for completeness ):- C:\LSYSTEM> compile test <ENTER> - Correct any errors ( using a text editor or word processor ) and repeat. C:\LSYSTEM> simulate test <ENTER> - Inspect the "test.RLT" file of tabular output results. - May stop the simulation cycle here if the tabular data is sufficient. C:\LSYSTEM> waveform test <ENTER> - Inspect graphical output of trace data. - Make modifications to the network description file "test.NWK". - Repeat simulation cycle from the compilation stage or finish. 4.2 Compiler options Once a network description file ( for example file.NWK ) has been created, the compiler can be invoked from the DOS command line by entering:- C:\LSYSTEM> compile file[.NWK] [switches......] <ENTER> where the switches and the file extension ".NWK" are optional parameters. The currently available switches are:- -l Generate a listing file, reporting any errors, (output file.LST). -e Generate an expanded file, macros fully expanded, (output file.EXP) -h Display a help screen, output highlights basic syntax rules. Entering C:\LSYSTEM> compile <ENTER> alone, will display the basic invocation instructions on the screen. 4.3 Simulator options Once the digital network description file has been compiled, and found to be error free, the simulator is invoked from the DOS command line by entering:- C:\LSYSTEM> simulate file <ENTER> No command line switches are available. 4.4 Waveform options After simulation, the digital network simulation results can be displayed graphically from the DOS command line by entering:- C:\LSYSTEM> waveform file [switches......] <ENTER> where the switches are optional parameters. All graphical display parameters, such as window sizing, are calculated, from automatically detected graphics adapter information, if no switches are used to specify a given display adapter. The waveform program also assumes that a mouse ( Microsoft mouse or a 100% compatible clone ) is not installed on your computer system. The available switches are:- -CGA_BL Set graphics to CGA 320 x 200 black and white mode. -CGA_C Set graphics to CGA 320 x 200 colour mode. -CGA_BH Set graphics to CGA 640 x 200 black and white mode. -EGA_C Set graphics to EGA 640 x 350 colour mode. -EGA_B Set graphics to EGA 640 x 350 black and white mode. -VGA_C Set graphics to VGA 640 x 480 colour mode. -VGA_B Set graphics to VGA 640 x 480 black and white mode. -HERC Set graphics to Hercules black and white mode. -MOUSE Activate MOUSE. Must only be used if a MOUSE driver is installed. Note all the graphics mode change switches can be interactively operated from the keyboard when the waveform graphics post processor program is running. 4.5 LSYSTEM batch files LS.BAT and LSM.BAT Two batch files are provided on the LSYSTEM master disks. These batch files automate the simulation cycle. Batch file LS.BAT assumes that your computer does NOT have a mouse installed. The reverse is true for batch file LSM.BAT. The complete LSYSTEM cycle can be invoked from the DOS command line by entering:- C:\LSYSTEM> LS file <ENTER> or C:\LSYSTEM> LSM file <ENTER> if you have a mouse installed. 5. Creating a digital logic network description file 5.1 The LSYSTEM logic network description language The LSYSTEM logic network description language is modelled on the SPICE language and has a similar format. The minimum information needed to be able to simulate the function and timing of a digital system is a set of statements which:- - Define the logic network topology - Give the the logic element types and parameters - Describe the primitive element models and MACRO structures - Define the signals driving the logic system - Specify what signals to monitor during the simulation - Control the simulation task Only one statement per line is allowed by LSYSTEM The LAST statement in the logic network description file must be a .END entry; NOTE NO space between the . and the E character. Any statement that begins with a * is assumed by LSYSTEM to be a COMMENT statement. Statements may be entered in either lower or upper case letters, and indeed a mixture of both forms is allowed, but please note LSYSTEM converts all letters to upper case so names entered, for example, as GATE1, gate1 or GaTe1 are identical. Logic element DELAY or RISE or FALL times must be entered as an INTEGER number of nano seconds. Logic element STRENGTH values or HIGH or LOW values must be entered as INTEGER percentages in the range 0% to 100%. The logic network description is a nodal representation of the digital system to be simulated. Each connection point between elements, these are called nodes, is allocated a unique name ( up to 16 characters long ). The total network is described in terms of the functional logic elements, from which it is built, and how these elements interconnect. The interconnecting points or nodes represent the functional elements input/output pins, for example, the following network has 4 nodes: A, B, C and D:- +-----+ +------+ I & I I 1 I A ----I I C I I I I---------I I-------- D B ----I I I I I I I I +-----+ +------+ This network would be described by saying that the two input AND gate has inputs A and B, with output C connected to the input of the buffer gate. The output of the buffer gate is D. 5.2 An example simulation At this stage in the description of the LSYSTEM CAD package an example simulation is introduced. The example has been chosen to illustrate a range of basic features provided by the software. 5.2.1 A synchronous BCD mod 16 counter SEE PRINTED USER GUIDE FOR DIAGRAM 5.2.2 The network description file - BCD16.NWK * Example 1 --- SYNCHRONOUS BCD MOD 16 COUNTER * This example illustrates the "FILE.NWK" structure * and a range of basic features provided by the * LSYSTEM CAD software. * .LIB DEFAULT.LIB ; Load the SHAREWARE default logic primitive library. * GEN1 CLOCK CLK0 PERIOD(500) ; Periodic clock generator. GEN2 PRESET CLK1 ; PRESET set to logic 1. GEN3 CLEAR CLK0 300 ; CLEAR changes from logic 0 to 1 at 300nS. GEN4 COUNT CLK0 600 ; COUNT changes from logic 0 to 1 at 600nS. GEN5 J1K1 CLK1 ; J1K1 input set to logic 1. * .macro jkff_cp_ne j clock k clear qn q preset ; JKFF negative edge triggered g1 clock clockn INV (delay=3) ; MACRO. ic1 clockn clear preset j k q qn jkff_cp_pe .endm * G1 CLOCK COUNT CLK AND2 (DELAY=6) ; Start of logic network IC1 J1K1 CLK J1K1 CLEAR QN1 Q1 PRESET jkff_cp_ne ; description. G2 Q1 QN4 J2K2 AND2 (DELAY=6) IC2 J2K2 CLK J2K2 CLEAR QN2 Q2 PRESET jkff_cp_ne G3 J2K2 Q2 J3K3 AND2 (DELAY=6) IC3 J3K3 CLK J3K3 CLEAR QN3 Q3 PRESET jkff_cp_ne G4 J3K3 Q3 J4 AND2 (DELAY=6) IC4 J4 CLK Q1 CLEAR QN4 Q4 PRESET jkff_cp_ne * .TIME 6500 6500 ; Simulation duration. * .PRINT PRESET CLEAR COUNT CLOCK Q1 Q2 Q3 Q4 J1K1 J2K2 J3K3 ; Trace node list * .END 5.2.3 File BCD16.LST ***************************** LSYSTEM V2.0 *************************** Logic network listing for compilation of BCD16.NWK 0001: * Example 1 --- SYNCHRONOUS BCD MOD 16 COUNTER 0002: * This example illustrates the "FILE.NWK" structure 0003: * and a range of basic features provided by the 0004: * LSYSTEM CAD software. 0005: * 0006: .LIB DEFAULT.LIB; 0007: * 0008: GEN1 CLOCK CLK0 PERIOD(500); 0009: GEN2 PRESET CLK1; 0010: GEN3 CLEAR CLK0 300; 0011: GEN4 COUNT CLK0 600; 0012: GEN5 J1K1 CLK1; 0013: * 0014: .macro jkff_cp_ne j clock k clear qn q preset; 0015: g1 clock clockn INV (delay=3); 0016: ic1 clockn clear preset j k q qn jkff_cp_pe 0017: .endm 0018: * 0019: G1 CLOCK COUNT CLK AND2 (DELAY=6); 0020: IC1 J1K1 CLK J1K1 CLEAR QN1 Q1 PRESET jkff_cp_ne; 0021: G2 Q1 QN4 J2K2 AND2 (DELAY=6) 0022: IC2 J2K2 CLK J2K2 CLEAR QN2 Q2 PRESET jkff_cp_ne 0023: G3 J2K2 Q2 J3K3 AND2 (DELAY=6) 0024: IC3 J3K3 CLK J3K3 CLEAR QN3 Q3 PRESET jkff_cp_ne 0025: G4 J3K3 Q3 J4 AND2 (DELAY=6) 0026: IC4 J4 CLK Q1 CLEAR QN4 Q4 PRESET jkff_cp_ne 0027: * 0028: .TIME 6500 6500; 0029: * 0030: .PRINT PRESET CLEAR COUNT CLOCK Q1 Q2 Q3 Q4 J1K1 J2K2 J3K3; 0031: * 0032: .END ***** NODE and MACRO related warnings ***** 5.2.4 File BCD16.EXP ***************************** LSYSTEM V2.0 *************************** * Expansion listing for compilation of BCD16.NWK .LIB DEFAULT.LIB; GEN1 CLOCK CLK0 PERIOD(500); GEN2 PRESET CLK1; GEN3 CLEAR CLK0 300; GEN4 COUNT CLK0 600; GEN5 J1K1 CLK1; *-------------------- .macro jkff_cp_ne j clock k clear qn q preset; *-------------------- g1 clock clockn INV (delay=3); *-------------------- ic1 clockn clear preset j k q qn jkff_cp_pe *-------------------- .endm G1 CLOCK COUNT CLK AND2 (DELAY=6); *IC1 J1K1 CLK J1K1 CLEAR QN1 Q1 PRESET jkff_cp_ne; G1_0 CLK $1_CLOCKN INV DELAY 3 IC1_1 $1_CLOCKN CLEAR PRESET J1K1 J1K1 Q1 QN1 JKFF_CP_PE G2 Q1 QN4 J2K2 AND2 (DELAY=6) *IC2 J2K2 CLK J2K2 CLEAR QN2 Q2 PRESET jkff_cp_ne G1_2 CLK $2_CLOCKN INV DELAY 3 IC1_3 $2_CLOCKN CLEAR PRESET J2K2 J2K2 Q2 QN2 JKFF_CP_PE G3 J2K2 Q2 J3K3 AND2 (DELAY=6) *IC3 J3K3 CLK J3K3 CLEAR QN3 Q3 PRESET jkff_cp_ne G1_4 CLK $3_CLOCKN INV DELAY 3 IC1_5 $3_CLOCKN CLEAR PRESET J3K3 J3K3 Q3 QN3 JKFF_CP_PE G4 J3K3 Q3 J4 AND2 (DELAY=6) *IC4 J4 CLK Q1 CLEAR QN4 Q4 PRESET jkff_cp_ne G1_6 CLK $4_CLOCKN INV DELAY 3 IC1_7 $4_CLOCKN CLEAR PRESET J4 Q1 Q4 QN4 JKFF_CP_PE .TIME 6500 6500; .PRINT PRESET CLEAR COUNT CLOCK Q1 Q2 Q3 Q4 J1K1 J2K2 J3K3; .END 5.2.5 File BCD16.INF ***************************** LSYSTEM V2.0 *************************** Information file for network BCD16.NWK Number of source lines compiled: 32 Number of nodes in network: 21 Number of trace nodes: 11 Number of logic components in network: 12 Number of excitation clocks: 5 Simulation length: 6500 Simulation display period: 6500 Number of primitives loaded: 63 Number of macros loaded: 1 Number of used macros: 1 Highest macro nesting: 1 --- S Y M B O L T A B L E --- {0001} $1_CLOCKN {0002} $2_CLOCKN {0003} $3_CLOCKN {0004} $4_CLOCKN {0005} CLEAR {0006} CLK {0007} CLOCK {0008} COUNT {0009} J1K1 {0010} J2K2 {0011} J3K3 {0012} J4 {0013} PRESET {0014} Q1 {0015} Q2 {0016} Q3 {0017} Q4 {0018} QN1 {0019} QN2 {0020} QN3 {0021} QN4 --- U S E D P R I M I T I V E T A B L E --- 0004 off AND2 0004 off INV 0004 off JKFF_CP_PE --- U S E D M A C R O T A B L E --- {0000} JKFF_CP_NE 5.2.6 Tabular results - file BCD16.RLT ******************************* LSYSTEM V 2.0 ****************************** Simulation Results for network file BCD16.FNC PCCCQQQQJJJ RLOL1234123 EEUO KKK SANC 123 ERTK Time..... (nS) T Startup condition 0: 0111XXXX0XX NC 1: 1000XXXX1XX NC 2: 1000XXXX1XX NC 3: 1000XXXX1XX NC 4: 1000XXXX1XX NC 5: 1000XXXX1XX NC 6: 1000XXXX1XX NC 7: 1000XXXX1XX NC 8: 1000XXXX1XX NC 9: 1000XXXX1XX NC 10: 1000XXXX1XX NC 11: 1000XXXX1XX NC 12: 1000XXXX1XX NC 13: 1000XXXX1XX NC 14: 1000XXXX1XX NC 15: 1000XXXX11X NC 16: 1000XXXX11X NC 17: 1000XXXX11X NC 18: 1000XXXX11X NC 19: 1000XXXX11X NC 20: 1000XXXX11X NC 21: 1000XXXX111 NC 22: 1000XXXX111 NC 23: 1000XXXX111 NC 24: 10000000111 NC 30: 10000000100 NC 250: 10010000100 NC 300: 11010000100 NC 500: 11000000100 NC 600: 11100000100 NC 750: 11110000100 NC 1000: 11100000100 NC 1018: 11101000100 NC 1024: 11101000110 NC 1250: 11111000110 NC 1500: 11101000110 NC 1518: 11101100110 NC 1524: 11100100111 NC 1530: 11100100101 NC 1536: 11100100100 NC 1750: 11110100100 NC 2000: 11100100100 NC 2018: 11101100100 NC 2024: 11101100110 NC 2030: 11101100111 NC 2250: 11111100111 NC 2500: 11101100111 NC 2518: 11101110111 NC 2524: 11100010111 NC 2530: 11100010100 NC 2750: 11110010100 NC 3000: 11100010100 NC 3018: 11101010100 NC 3024: 11101010110 NC 3250: 11111010110 NC 3500: 11101010110 NC 3518: 11101110110 NC 3524: 11100110111 NC 3530: 11100110101 NC 3536: 11100110100 NC 3750: 11110110100 NC 4000: 11100110100 NC 4018: 11101110100 NC 4024: 11101110110 NC 4030: 11101110111 NC 4250: 11111110111 NC 4500: 11101110111 NC 4518: 11101111111 NC 4524: 11100001111 NC 4530: 11100001100 NC 4750: 11110001100 NC 5000: 11100001100 NC 5018: 11101001100 NC 5250: 11111001100 NC 5500: 11101001100 NC 5524: 11100000110 NC 5530: 11100000100 NC 5750: 11110000100 NC 6000: 11100000100 NC 6018: 11101000100 NC 6024: 11101000110 NC 6250: 11111000110 6500: 11101000110 5.2.7 A screen dump of the BCD16 Network timing diagram SEE PRINTED USER GUIDE FOR DIAGRAM 5.3 The structure of the LSYSTEM network description file The following template outlines the structure of the LSYSTEM network description file:- * Title and header information * - entered as a series of comments. .LIB DEFAULT.LIB ; Logic primitive library files loaded * using the .LIB directive. .INCLUDE DEFAULT.MAC ; Macro library file loaded using the * .INCLUDE directive. * Other macro definitions next. .MACRO ............ ............ .ENDM * Clock and logic function statements next. ........................... .TIME ............. .PLOT or .PRINT statements. .END 5.4 Logic primitive libraries Access to a library of primitive logic element models is available in LSYSTEM. To load a library, the statement .LIB library_name is entered near the beginning of the LSYSTEM network description file. At least one model library must be loaded for LSYSTEM to function. Please note a primitive library must be loaded before any models in the library are used. Only one library can be loaded per .LIB command. However, as many .LIB statements may be specified as required, for example:- .LIB default.LIB ; load the SHAREWARE default model library. .LIB gates.LIB ; only supplied to registered users. .LIB memory.LIB ; again only supplied to registered users. 5.4.1 Using primitives All primitive model definitions have the same structure, although some of the information is redundant, depending on the primitive type. Three basic types of primitive model currently exist, they are - Combinational logic elements. - Clocked sequential logic elements. - memory elements. Their use is strictly controlled by, for example, nodal positioning, triggering edges, and asynchronous input polarities. Primitive models are based on a look-up table. Inputs specified in the model definition form part of the look-up table index. Hence, it is important that input nodes be used in the correct order. The structure of a primitive library file is described in detail in Appendix B. Information is also provided to help LSYSTEM users construct their own primitive libraries. 5.4.2 Combinational primitives Combinational model primitives have one type of input, this is one or more, non-clocked, logic inputs. A primitive's outputs have a direct relationship to to these inputs since the model is purely a combinational function. Information specifying a primitive ALWAYS has the following sequence:- - Input nodes, in the order given in the primitive definition. - Output nodes, again in the order given in the primitive definition. - The model name. Hence, a functional element description for a primitive type called NAME has the format:- Element IN1 IN2 IN3 IN4 .... OUT1 OUT2 OUT3........ NAME . ........... Reference Element name to identify the logic component. where each item in the list is separated by one or more spaces. 5.4.3 Sequential primitives Sequential primitives are a little more complex than combinational ones. Using them is very advantageous though, since it allows a degree of FUNCTIONAL SIMULATION, which simplifies and speeds the simulation process enormously. When modelling a complex digital system, it is often sufficient to just use a functional box to represent an element or a sub-unit of the digital network, for example a D-TYPE flip flop, or an 8bit up/down counter, instead of having to code the entire logic system as gate level primitives. The maximum internal state bits for a sequential primitive is 8, yielding 256 maximum internal states. This is quite sufficient for most purposes and restricts look-up tables to a moderate size ( a practical consideration due to the DOS 640k memory limit). Sequential primitives have FOUR types of input, these must be specified in the following order:- - Clock input node. - Combinational input nodes, these DO NOT effect the internal state, for example an OUTPUT ENABLE which switches a logic element into tri state output mode. - Asynchronous ( active low ) input nodes, for example CLEAR and PRESET on a flip flop. - Synchronous clocked ( rising edge triggered ) input nodes, for example J and K on a flip flop. The input node names are then followed by the output node list, and finally the name of the logic primitive. Hence. for example a 4 bit counter would be described as:- IC1 CLK OE CLEAR LOAD A B C D Qa Qb Qc Qd TC 4CountLoad 5.4.4 RAM primitives INFORMATION ONLY PROVIDED TO REGISTERED LSYSTEM USERS 5.4.5 ROM primitives INFORMATION ONLY PROVIDED TO REGISTERED LSYSTEM USERS 5.4.6 Default primitive library list. 1. EL IN1 IN2 OUT AND2 (DELAY=9 LOW=50 HIGH=40) 2. EL IN1 IN2 OUT OR2 (DELAY=9 LOW=50 HIGH=40) 3. EL IN OUT RES (DELAY=1 STRENGTH=10) 4. EL IN OUT INV (DELAY=9 LOW=50 HIGH=40) 5. EL CLK CLR PR J K Q NQ JKFF_CP_PE (RISE=9 FALL=15 LOW=50 HIGH=40) 6. EL CLK CLR PR D Q NQ DFF_CP_PE (RISE=9 FALL=15 LOW=50 HIGH=40) 7. EL IN1 IN2 IN3 IN4 OUT NAND4 (DELAY=9 LOW=50 HIGH=40) 8. EL OE IN OUT TBUF (RISE=13 FALL=17 LOW=50 HIGH=40) 9. EL I1 I2 I3 I4 I5 OUT AND5 (DELAY=9 LOW=50 HIGH=40) THE DEFAULT LIBRARY PROVIDED TO REGISTERED LSYSTEM USERS CONSISTS OF 65 PRIMITIVES ---- SEPARATE GATE, FLIP FLOP, OPEN CIRCUIT COMPONENT AND TRI STATE DEVICE LIBRARIES ARE ALSO INCLUDED ON THE LSYSTEM PRODUCTION MASTER DISKS. 5.5 The include file command - .INCLUDE Include files are standard text files that are opened and read by LSYSTEM compiler into the main network description file as it is being compiled. As many files as required can be defined for inclusion, although only ONE per .INCLUDE directive. Include files can be nested to 20 levels deep, i.e., an include file can call another include file which can call another include file ...... up to 20 levels. The syntax for the include command is:- .INCLUDE FILE_1.EXT .INCLUDE FILE_2.EXT The main use for this directive is for loading previously defined MACROS. A file containing some useful macros. prepared for direct inclusion into any network description, has been included on the LSYSTEM disks. The macro file is called DEFAULT.MAC.